1. Field of the Invention
The present invention relates to a technique for operating a semiconductor memory at high speed. In particular, the present invention relates to a technique for transmitting address signals supplied from exterior to internal circuits earlier.
2. Description of the Related Art
In general, address signals supplied to a semiconductor memory are received by address buffers before they are held in latch circuits and supplied to decoders. The latch circuits are controlled by a control signal, such as a chip select signal, which are supplied from exterior. Then, the decoders decode the held address signals to select a word line and a column line corresponding to the memory cell to operate, so that data held in the memory cell is read out. Alternatively, data is written to the memory cell. Meanwhile, in a semiconductor memory having no address-signal latch circuits, address buffers are controlled by the control signal.
Japanese Patent Laid-Open Publication No. Sho 61-153894 and others have disclosed semiconductor memories in which address signals are transmitted to internal circuits earlier for the sake of reduced access time.
In a semiconductor memory of this type, a control signal controls decoders, not address buffers. Address signals supplied from exterior are not controlled by the control signal, but transmitted directly to the decoders. This advances the transmission of the address signals to the internal circuits, thereby reducing access time.
More specifically, in the above-mentioned publication, the control signal controls both the address buffers and the decoders as to column address signals which have smaller influence on the access time, whereas it controls only the decoders as to row address signals which have greater influence on the access time.
Nevertheless, no specific technique has been heretofore disclosed on how to control both the address buffers and the decoders with the control signal so that the address signals are transmitted to internal circuits earlier.
Moreover, when the control signal controls not the address buffers but the decoders alone, the address signals supplied from exterior are constantly transmitted to the decoders. Accordingly, if the address signals undergo a change due to noises and the like occurring on the system board during an activation period of the decoders, the change can be transmitted directly to the decoder (such as a row decoder). As a result, a plurality of word lines might be simultaneously selected for malfunction.
It is an object of the present invention to transmit address signals supplied from exterior to internal circuits earlier, thereby reducing the access time of the semiconductor memory.
It is another object of the present invention to avoid malfunctions resulting from address signal noises.
According to one of the aspects of the semiconductor memory in the present invention, an address input circuit transmits an address signal supplied from exterior to the internal circuit before a control signal operating a memory cell is activated. The address input circuit inhibits the reception of a new address signal after the control signal is activated. A decoder is inactivated before the activation of the control signal. Therefore, the address signal transmitted from the address input circuit to the decoder will not be decoded at this time. The decoder is activated after the activation of the control signal, to decode the address signal. Thus, making use of the address signal reaching the decoder before the activation of the control signal, the decoder starts operating at an earlier timing of the operation cycle, outputting a decoding signal. This leads to reduction in access time.
The reception of a new address signal is inhibited after the activation of the control signal. This precludes the decoder from decoding incorrect address signals resulting from noises or the like. In other words, the decoding of a plurality of address signals in a single operating cycle is avoided.
According to another aspect of the semiconductor memory in the present invention, the address signal supplied before the activation of the control signal is held in a holding part formed in the address input circuit. Thus, after the reception of a new address is inhibited, the address signal received in advance is surely supplied to the decoder.
According to another aspect of the semiconductor memory in the present invention, the reception of the address signal and the operation of the decoder are controlled by an output enable signal for controlling the external output of data read from the memory cell. This means reduction in read cycle time.
According to another aspect of the semiconductor memory in the present invention, the reception of the address signal and the operation of the decoder are controlled by a write enable signal for controlling the acceptance of data to be written to the memory cell. This means reduction in write cycle time.
According to another aspect of the semiconductor memory in the present invention, the reception of the address signal and the operation of the decoder are controlled by a chip enable signal for activating an internal circuit into an operable state. This means reductions in read cycle time and write cycle time.
According to another aspect of the semiconductor memory in the present invention, the address signal receiving operation and the decoding operation are surely controlled even in a clock asynchronous memory.
According to one of the aspects of the method of operating a semiconductor memory in the present invention, an address signal supplied from exterior is transmitted to a decoder before the activation of a control signal operating a memory cell. Here, the decoder is inactivated. This prevents a decoding signal obtained by decoding the address signal from being output before the activation of the control signal. Subsequently, after the activation of the control signal, the reception of a new address signal is inhibited, and the decoder is activated at the same time. Therefore, as has been described above, the decoder starts operating at an earlier timing with reduction in access time. Moreover, the decoder is prevented from decoding incorrect address signals.